This invention relates to PRIMOS devices, and to a method of fabricating the same.
As is well known, the semiconductor industry continually seeks the fabrication of MOS devices so as to increase density, speed and reliability thereof, meanwhile achieving high device yield. The achievement of high density and speed require extremely small dimensioning, use of high conductivity components, low overlap capacitance, minimum alignment and dimension tolerances, and the use of multi-level interconnections.
Achievement of high yield and reliability relies on such factors as: use of high quality bulk silicon, controlling of device and parasitic parameters, use of high integrity conductors, a minimum number of processing steps, use of radiation hardness techniques, the ability to passivate devices, and minimum topology.
Certain of these advantages are provided in a UMOS device of the type disclosed in the technical paper entitled "GROOVED GATE MOSFET" by Nishimatsu, et al, published in 1976. As shown in that document, the u-shaped oxide in cross-setion is generally uniform in thickness throughout its full length on either side of and under the gate. This provides the problem that overlap capacitance is greater than desirable. The structure, as constructed, with polysilicon as the doping sources, must suffer control problems when forming the junctions in the bulk silicon. With polysilicon being a major portion of the groove sides, the oxide integrity grown thereon would be a major problem. Furthermore, the structure as proposed is not planar with the field oxide surface.